By Johan Huijsing, Michiel Steyaert, Arthur H.M. van Roermund
This 10th quantity of "Analog Circuit layout" concentrates on three issues: Scalable Analog Circuits, High-Speed D/A Converters, and RF strength Amplifiers. every one subject is roofed through 6 papers, written through foreign famous specialists on that subject. those papers have an instructional nature aimed toward bettering the layout of analog circuits. The booklet is split into 3 elements: half I, Scalable Analog Circuit layout describes in 6 papers problems with: scalable high-speed layout, scalable high-resolution mixed-mode ADC and OpAmp layout, scalable high-voltage layout for XDSL, scalability of wire-line entrance ends, reusable IP analog layout, and porting CAD analog layout. half II, High-Speed D/A Converters describes in 6 papers problems with: creation to high-speed D/A converter layout, retargetable 12-bit 200-MHz CMOS present steerage layout, high-speed CMOS D/A converters for upstream cable purposes, static and dynamic functionality boundaries, the linearity problem of D/A converters for communications, and a 400-MHz, 10-bit charge-domain CMOS D/A converter for low-spurious frequency synthesis. half III, RF energy Amplifiers describes in 6 papers problems with: procedure points, evaluation and trade-offs, linear transmitter architectures, GaAs microwave SSPAs, Monolithic transformer-coupling in Si-bipolar, and RF energy amplifier layout in CMOS. "Analog Circuit layout" is an important reference resource for analog layout engineers and researchers wishing to maintain abreast with the newest advancements within the box. the educational assurance additionally makes it compatible to be used in an enhance layout path.
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Extra resources for Analog Circuit Design: Scalable Analog Circuit Design
Fig. 6V supply voltage for the year 2010 . To get a feeling of how process-parameters have changed over time and will change in the near future, Table 1 gives an overview of 14 different processes, ranging from down to of which only the last two are predictions (data from [15, 17, 18, 21]). The Supply Voltage Oxide Thickness Threshold Voltage and Matching parameter of these 14 processes are plotted on a log-log scale in Fig. 3. 0V In smaller technologies, scales roughly linear with minimum feature size (although it follows a 59 staircase function).
32, pp. 1896-1906, Dec. 1997 18) “Tree Structure for Mismatch Noise-Shaping Multibit DAC” Keady and Lyden, Elec. Letters, Vol. 33, pp. 1431-1432, Aug. , Proc. European Solid-State Circuits Conference, Southampton, 1997 20) “Delta-Sigma Data Converters” Norsworthy, Schreier and Temes, IEEE Press, 1997 21) “A Monolithic 19 bits 800kHz Low Power Multibit Sigma Delta Modulator CMOS ADC Using Data Weighted Averaging” Nys and Henderson, Proc. European Solid-State Circuits Conference, pp. 252-255, Southampton, 1996 22) “A Low Oversampling Ratio 14-b 500kHz Delta-Sigma ADC with a Self-Calibrated Multibit DAC” Baird and Fiez, IEEE Jnl.
The low frequency path in this design can use any of the wide variety of chopping and auto-zeroing methods. This field has itself been the subject of a comprehensive review paper so will not be discussed further here . It is thus suited to applications where the input common mode range and frequency spectrum are well defined and thus known to lie within the architecture’s limitations. 35um and 3v supply. 35um driver application delivers 4v p-p (differential) into just 8 ohms load with a class A/B output stage with order 10mm wide output MOS devices with –75dB distortion at 140kHz [Hurrell – private communication].